Solutions for Process Challenges on Fan-Out Wafer Level Packaging of Electronic-Photonic Integration

The integration of electronic and photonic components on the same package is gaining more significance in fields such as high-performance computing and hyper-scale data centres for high bandwidth communication, reducing power consumption, and improving overall system performance. Here, a Mold first Fan-out Wafer Level Packaging was chosen to integrate a Photonic Integrated Circuit Chip consisting of special structures such as cavities together with other electronic Integrated Circuit Chips. Few process challenges are encountered in this development for embedding Photonic Integrated Circuit Chip and other ICs inside mold, such as (a) Molding tape residue inside the cavity during the reconstitution process (b) Dielectric layers coverage on Epoxy Mold Compound at the area between Photonic Integrated Circuit Chip and other adjacent Integrated Circuit Chip, (c) Photoresist coverage at cavity area. This study explores resolutions to tackle the aforementioned process challenges during fabrication.