All-Digital Background Calibration of a Pipelined-SAR ADC Using the “Split ADC” Architecture

A split based all-digital background calibration for an 18-bit pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this paper. The "split ADC" architecture is exploited to eliminate the signal interference and accelerate the convergence speed of the calibration. The output difference of two channels continuously drives the background calibration algorithm to estimate and correct the error caused by nonlinearities. To guarantee the validity of calibration with different inputs, shuffling scheme is adopted in capacitor array. Different dither signals are injected into two channels to achieve faster convergence, especially under the DC input. In the meanwhile, enough redundancy is introduced to capacitor array to avoid the decrease of input range caused by dither signal. A 4-bit coarse ADC is exploited to alleviate conversion time and provide dither injection. A behavior level model with various nonideal factors is established in MATLAB to prove the availability of calibration for an 18-bit pipelined-SAR ADC. The simulation shows that the ENOB achieves 16.5-bit, the SNDR is increased from 52.4 dB to 100.9 dB and the SFDR is improved from 72.3 dB to 119.6 dB.