A 10-bit SAR ADC with adaptive VCO-based comparator for sensor chip

This paper presents a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with adaptive Fig. 1. 10-bit SAR ADC with the proposed AVB comparator voltage-controlled oscillator (VCO)-based comparator for sensor chip. The proposed adaptive VCO-based (AVB) comparator can improve the speed in large differential input, and reduce the power of the phase detector in small differential input. The simulation results show that the proposed SAR ADC achieves 57.68-dB SNDR and consumes 140 nW under a supply of 0.6-V at the Nyquist input rate, resulting in a Walden Figure-of-merit (FoM) with 11.1 fJ/conversion-step in a 180nm CMOS process.