A 220nA bandgap reference with 80dB PSRR targeting energy harvesting

For emerging high volume applications such as wireless sensor networks, energy harvesting, or consumer biometrics, bandgap voltage references in CMOS may be viewed in a more favorable light by semiconductor manufacturing due to their low cost, ruggedness, and availability of the predictable parasitic bipolar junction transistor (BJT). To generate a bandgap voltage (VBG) reference with a near zero temperature coefficient (TC), a BJT's base-emitter voltage (VBE) with a negative TC is added to a gained-up thermal voltage (VT) with a positive TC. However, ultra low power applications prohibit use of conventional bandgaps because of the impractically large passive resistors they require to make their V _T 's gain factor (g) in V _BG = V _BE + g.V _T . One of the contributions of the proposed reference is to eliminate the large passive resistor in an ultra low power bandgap reference. Batteryless and wireless electronics, in general, may be subject to less orderly power supply patterns. To guard band against jittery supply and disorderly power up patterns, especially in mission critical bioelectronics applications, another contribution of the proposed design is that the positive feedback loop associated with bandgap's amplifier (that is vulnerable to transients) can be eliminated here without deterring overall performance. Ultra low currents are generally accompanied with increased noise. Additional contribution of this bandgap's topology is that its noise is reduced via dominant use of PMOSFETs, with low 1/f noise, in pertinent signal paths. Lastly, the operating currents of the entire bandgap is mostly independent of threshold voltage (V _TH ) and chiefly a function of mobility, u, that benefits manufacturability and die yield because u is more tightly controllable (compared to poly resistance or V _TH , for example). This bandgap consumes about 220 nA of current. Monte Carlo (MC) and worst case (WC) simulations indicate the following specifications are achievable: temperature coefficient (TC) of about 14 ppm / C over a 100C temperature range, voltage coefficient (VC) of about 0.02% / V, power supply rejection ratio (PSRR) of about negative 80dB with 1.5V <; V _DD <; 2.5 V. Die size is roughly 100um×180um in standard 0.18u digital CMOS.