Dynamic Comparator Design for High Speed ADCs

In an analogue to digital converter (ADC) circuit, comparators are one of the most critical components. ADCs, on the other hand, are frequently utilized in data acquisition systems and must be able to record analogue signals quickly. ADCs are also utilized indefinitely, necessitating minimal power consumption in order to extend battery life. In order to deal with this situation, our project created a comparator that had to be accurate and power effective. The Dynamic comparator (DC) is meant to have a highspeed performance and lower power consumption. The Charge Sharing DC and the Strong-Arm DC are two techniques that were compared and analyzed in order to develop a high-speed dynamic comparator. Cadence software was used to design the circuit, which employs a 0.18um CMOS technology. The simulation results reveal a clock frequency of 100 MHz at 1.8V supply voltage. 50 millivolts chosen as the resolution. The optimum topology of the design can reduce propagation delay, area, and power consumption with better performance.