Suppression and Optimization of 32G serdes power noise for FCBGA Packaging

As the chip manufacturing, process is getting closer and closer to the physical limit, people begin to shift their attention from the manufacturing process to the packaging level, trying to reduce the chip area and increase the circuit scale through the design of advanced packaging to continue Moore’s Law. Therefore, advanced packaging also integrates more and more IP cores, which puts forward higher design requirements for SI, PI and EMC in high-speed chips. This paper is mainly aimed at the problem that the power noise of the 32Gbps serdes IP exceeds the standard. Combined with the analysis of the package PDN impedance and the spectrum analysis of the current CPM model, a modification scheme of the package power supply design and capacitor optimization are proposed. The difficulty of the problem is the PDN impedance resonance peek at 1GHz. The resonance peak of GHz is generally difficult to optimize on the package, and can only be solved in the DIE, and this paper provides an optimization method on the package to suppress the PDN resonance peak at 1GHz, which is a solution to the resonance peak above GHz. This paper provides a way of thinking and reference.