Reliability Implications of Thermo-Mechanically and Electrically Induced Interfacial Sliding of Through-Silicon Vias in 3D Packages

In conjunction with micro bumps, Through-Silicon-Vias (TSVs) are used for die stacking, leading to reduced footprints and a higher performance due to shorter communication bus-length. However the large difference between the thermal expansion of silicon and copper and an increased temperature of the die stack due to Joule heating lead to shear stress at the interface between TSV and substrate. Temperature activated interfacial diffusion in combination with the shear stress leads to diffusional interfacial sliding, resulting in TSV pro- or intrusion. In addition, electromigration (EM) at the interface leads to TSV motion. Against this background the protrusion/intrusion of Cu TSVs (ø 10 μm, length 100 μm) during fast and slow rate thermal cycling (TC) and during EM experiments was investigated. Parallel to the experimental investigation a finite element analysis (FEA) was performed to study the micro-mechanical responses of Cu-filled TSV during thermal cycling. For this purpose interfacial sliding was incorporated into the FE model by diffusional creep mechanism. The FE model captures the main features being observed in experiments such as stress hysteresis and intrusion/protrusion of the TSV relative to Si substrate.