Study of precisely controlled selective isotropic quasi-ALE of SiGe

In gate-all-around nanosheet (GAA-NS) transistor manufacturing, the SiGe layer plays an important role as a sacrificial layer, requiring precisely controlled and highly selective isotropic etching. In our previous work, we proposed a novel isotropic selective quasi-atomic layer etching (quasi-ALE) method based on O₂ plasma self-limiting oxidation and CF₄/C₄F₈ self-limiting selective etching. A vertical nanowire transistor with a diameter less than 20nm and an accuracy error less than 0.3nm has been developed. In this paper, we adopt this method to cavity etching of horizontally stacked nanosheets, using an ICP source to perform self-limiting oxidation of the SiGe layer followed by self-limiting selective removal of oxide (a two-step self-limiting cycle) to form inner spacer cavity. Experimental results show that compared with the strong dependence of the etching amount on SiGe thickness and Ge composition in traditional ICP dry etching, the quasi-ALE technology tends to weaken this size and concentration loading effect due to the self-limiting of each cycle reaction. In addition, we also demonstrated the latest progress in corresponding ALE simulation using a commercial feature-scale plasma process simulator named PEGASUS. The simulation results show that the SiGe etching amount per cycle (EPC) is about 0.3nm, which is basically consistent with the experimental results. This quasi-ALE method demonstrates promising performance for preparing GAA device channels, nanosensors, and other application in future.