A 280-mW, 112-Gb/s PAM-4/NRZ Transceiver for Low-Power IOs in 5-nm FinFET Technology

This article presents an ultralow-power and compact 112-Gb/s pulse-amplitude modulation 4-level (PAM-4)/NRZ transceiver in 5-nm FinFET process. The receiver (RX) features a quarter-rate architecture with a$G_{m}$-TIA-based analog front end (AFE), a three-tap feed-forward equalizer (FFE), and an 11-tap decision feedback equalizer (DFE). A key feature of this design is an AFE tuning scheme that corrects the first and second post-cursor inter-symbol interference (ISI), simplifying the DFE and slicer design to significantly reduce power. The RX employs an integral non-linearity (INL) canceling phase interpolator (PI) to generate low-jitter quadrature clocks for baud-rate clock and data recovery (CDR). The transmitter (TX) utilizes a half-rate 40:1 multiplexer (MUX) followed by a 7-bit digital-to-analog converter (DAC)-based source-series termination (SST) driver. A single low-jitter phase-locked loop (PLL) is shared between four transceiver lanes. Operating from a single 0.8-V supply, the transceiver consumes only 280 mW/lane and reliably compensates for up to 35 dB of channel loss at Nyquist with a BER${\lt }~1$e−6. This work achieves a best-in-class figure of merit (FOM) of 0.07 pJ/bit/dB compared with previously reported 112-Gb/s transceivers, making it an ideal solution for next-generation, high-density interconnects.