均衡器
CMOS芯片
自适应均衡器
计算机科学
电子工程
放大器
偏移量(计算机科学)
符号间干扰
误码率
频道(广播)
控制理论(社会学)
工程类
电信
人工智能
程序设计语言
控制(管理)
作者
Jonathan E. Proesel,Timothy Dickson
摘要
A power-efficient equalizing serial receiver, including a 2-stage continuous-time linear equalizer (CTLE) and 1-tap decision feedback equalizer (DFE), is reported operating at data rates of up to 20 Gb/s. The DFE adopts a half-rate speculative architecture without explicit summing amplifiers by injecting offset-controlling currents directly into StrongARM sampling latches. At 20 Gb/s, a PCB trace with 26.3dB of loss is equalized while consuming 13.2mW (0.66 pJ/bit).
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