Tradeoff of energy and hardware resources in high level synthesis

This paper studies the energy consumed in VLSI systems that have multiple-stage functionally pipelined datapath. A two-process approach is then proposed to synthesize such datapath by partitioning the datapath into multiple pipelined stages that can be operated with multiple frequencies and multiple supply voltages, aiming to reduce energy consumed by the datapath. Experimental results show that the proposed approach is effective for reducing energy.