稳健性(进化)
计算机科学
推论
卷积神经网络
现场可编程门阵列
硬件加速
计算机工程
嵌入式系统
重新使用
卷积(计算机科学)
断层(地质)
故障注入
加速度
计算
深度学习
人工神经网络
推理机
延迟(音频)
蒸馏
自动化
电效率
香料
控制工程
实时计算
人工智能
能源消耗
特征提取
核(代数)
机器学习
电子设计自动化
故障检测与隔离
可靠性工程
计算复杂性理论
算法设计
逻辑门
统计推断
计算机硬件
功率消耗
逻辑综合
作者
Kehui Zhu,Xinming Li,Z.-Y. Liu,Jinrui Zhang,Yuzhou Wang
标识
DOI:10.1109/tim.2026.3666004
摘要
Deep learning has achieved significant progress in industrial equipment fault diagnosis. However, large-scale models are challenging to deploy in industrial settings that require low power consumption and high portability. Moreover, the high latency introduced by model inference reduces the efficiency of real-time fault detection. In this study, we propose a lightweight fault diagnosis network and develop a convolutional neural network (CNN) acceleration for field-programmable gate array (FPGA) deployment. Firstly, a progressive knowledge distillation strategy is proposed to reduce the discrepancy between the teacher and student networks, thereby enhancing the overall distillation effectiveness. Experimental results demonstrate that the distilled student network, with only 1.32K parameters, achieves remarkable diagnostic performance and robustness against noise. Secondly, we designed an FPGA-based CNN accelerator. This design integrates the Winograd algorithm with a systolic array architecture to substantially accelerate convolution operations while reducing resource consumption. Moreover, parallel computation and module reuse are employed to further enhance inference throughput. Experimental results demonstrate that, compared to CPU and GPU implementations, the proposed accelerator achieves speedups of 142.8× and 1.40×, respectively, while reducing power consumption by 14.5× and 30.2×. Compared to state-of-the-art FPGA accelerators, the proposed design provides an approximate 16% improvement in inference speed. The deployed models achieve F1-scores exceeding 98% on two bearing datasets, validating the proposed method’s capability for real-time fault diagnosis in low-power industrial environments.
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