Towards Compute Capacity Maximization in Constrained Interconnect Multi-Chip Quantum Computing

Quantum computing holds promise for performing optimization tasks efficiently, but its potential is currently hindered by the presence of noisy qubits and short coherence times in noisy intermediate scale quantum devices, limiting their practical use to small-scale problems. As a solution, multi-chip quantum computing presents an attractive alternative. We have developed two multi-chip mapping methods that maximize compute capacity utilization of quantum processing units (QPUs) while addressing their limited coherence times and the transmission rates of quantum interconnects. These methods assess critical parameters of QPUs and interconnects in a multi-chip quantum network, enabling optimal assignment of quantum gates in a quantum algorithm onto the network. Our methods produce runnable subcircuits, mapped to a minimum number of capacity-maximized QPUs while achieving high-fidelity multi-chip quantum computing.