0.5 μm Pitch Wafer-to-wafer Hybrid Bonding at Low Temperatures with SiCN Bond Layer

薄脆饼 晶片键合 材料科学 图层(电子) 光电子学 复合材料
作者
Kai Ma,Nikolaos Bekiaris,Ching‐Hsiang Hsu,Lei Xue,Sesh Ramaswami,Taotao Ding,Gernot Probst,Tobias Wernicke,Thomas Uhrmann,Markus Wimplinger
标识
DOI:10.1109/ectc51529.2024.00061
摘要

3D integration by adopting wafer-to-wafer (W2W) or chip-to-wafer (C2W) direct bonding techniques scales up interconnect density. Heterogenous integration enabled by direct bonding technology brings wafers or chips with different functionalities into close proximities, thus providing system performance benefits such as faster I/O speed and lower power consumption, etc. We have previously reported a robust integration flow with high electrical yield for 300mm wafer-to-wafer hybrid bonding with SiCN bonding interface at 0.5 μm bond pad pitch [1]. SiCN was chosen as the bonding layer to harness its excellent Cu diffusion barrier property, in addition to the superiorly high bonding energy demonstrated by the SiCN films with optimized compositions. High yield electrical results were achieved by bonding the wafers at room temperature, followed by a 350°C post-bonding anneal to allow for Cu expansion and diffusion to form gap-free Cu-Cu bonds. In certain applications, such as a D2W HBM4 bonding, when heterogeneously integrating DRAM, logic, and other functions together, or when temporary bonding adhesives are used in the flow, lowering thermal budget is necessary for DRAM data retention or for compatibility with the adhesives. In this work, we attempted to use a wafer-to-wafer hybrid bonding test vehicle to explore the possibility of scaling down the post-bonding anneal temperatures from 350°C to 200°C. We carefully optimized SiCN film compositions at different deposition temperatures and achieved high bonding energies at post-bonding anneal temperatures ranging from 200°C to 350°C. The Cu/SiCN bonding surface topography control by Chemical Mechanical Polishing (CMP) is the most crucial process factor to ensure good bonding quality, especially when there is less thermal energy available for Cu diffusion at low temperatures. A desired Cu recess profile (< 2 nm dishing and < 1 nm WIW variation) and smooth SiCN surface finish (< 2 Å RMS roughness) were achieved by optimizing the Cu/SiCN CMP process on Applied Materials’ Reflexion® LK Prime system. With this test vehicle, we electrically achieved bonding via chain resistance distribution comparable to that of the 350°C samples, when annealed at lower temperatures down to 200°C.
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