Integrated Thermal Management Strategies for 3D Chip Stacking with Through-Silicon Vias (TSV)

This study investigates the thermal management challenges associated with three-dimensional chip stacking, exacerbated by the use of thermally non-conductive adhesives and reduced thermal diffusion. Despite these hurdles, the integration of 3D stacked circuits with through-silicon vias (TSV) holds promise for electronic system miniaturization and performance enhancement. To address these issues, an innovative approach employing a compact thermal model has been developed to accurately predict temperature distribution. Finite element simulations have shown excellent agreement with results from other methods, with errors below 5.6% for peak temperatures. This approach enables rapid and effective assessment of thermal parameters, providing crucial insights for future designs and applications. The study also focuses on enhancing thermal management for 3D TSV technology by proposing a detailed methodology for implementing thermal simulations and evaluating thermal management. It further introduces a 3D resistive thermal circuit model and utilizes COMSOL finite element tool to model and simulate 3D stacks. Lastly, it plans to implement this model using VHSIC hardware description language (VHDL) for logical and functional simulations, aiming to optimize thermal management for 3D TSV technology.