德拉姆
节点(物理)
过程(计算)
材料科学
接触过程(数学)
光电子学
电子工程
计算机科学
工程类
物理
统计物理学
操作系统
结构工程
作者
Seungwan Jang,SoYoung Kim
标识
DOI:10.1109/ted.2024.3474609
摘要
Due to the rapidly shrinking size of the dynamic random access memory (DRAM) cell, mitigating the characteristic degradation caused by the local distribution of the contact size is becoming a greater challenge. The size of the DRAM storage node contact (SNC) determines the amount of phosphorus (P) dopant that diffuses into the active region. Smaller contact size limits the out-diffusion of P dopant and increases the SNC resistance ( ${R}_{\text {SNC}}$ ) and overlap resistance ( ${R}_{\text {OV}}$ ). This results in characteristic degradation of the last data into row precharge time (tRDL). For larger contact sizes, the out-diffusion of P dopant expands to increase the gate-induced drain leakage (GIDL) and decrease the retention time (tRET). To address this tradeoff issue, we propose a multilayer contact design using a combination of high and low P concentrations, where the doping concentration changes as a function of SNC size. We used atom probe tomography (APT), electrical test (ET) on test element groups (TEGs), and electrical die sorting (EDS) to analyze the correct formation and characteristic performance improvements of the proposed structures. Using the proposed design structure, the tRET and tRDL characteristics improved by 3.9% and 34.7%, respectively.
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