放大器
晶体管
高电子迁移率晶体管
有功负荷
电气工程
调制(音乐)
拓扑(电路)
功率(物理)
电子工程
电压
材料科学
物理
工程类
CMOS芯片
声学
量子力学
作者
Amirreza Alizadeh,Saleh Hassanzadehyamchi,Ali Medi,Sayfe Kiaei
出处
期刊:IEEE Transactions on Circuits and Systems I-regular Papers
[Institute of Electrical and Electronics Engineers]
日期:2020-05-08
卷期号:67 (10): 3364-3377
被引量:20
标识
DOI:10.1109/tcsi.2020.2991184
摘要
In this paper, the performance of the class-J mode power amplifier (PA) is studied when an auxiliary network performs active load modulation on the main transistor. Load modulation is realized by injecting an additional class-C like current with conduction angle of α to the drain node of the main transistor. The injected current employs a phase shift of φ with respect to the half-sinusoidal current of the main transistor, and its maximum value is tuned with the size of the transistor used in the auxiliary network. Detailed theoretical formulations are presented for the optimal load impedances of the PA at the fundamental and second-harmonic frequencies. Furthermore, the output power and drain efficiency of the PA are derived, and it is shown that the drain efficiency of the proposed PA can be as high as 96.8% in theory. The optimal values of α and φ for improving the drain efficiency of the load-modulated class-J PA are obtained, and a design methodology is also proposed to choose the optimal size of the transistor employed in the auxiliary network. To verify the theoretical derivations, a proof-of-concept 0.83 W class-J PA was designed and fabricated in a 0.25 μm GaAs pHEMT process. The designed PA occupies 3.19 mm 2 die area, and it achieves 71% drain-efficiency and 50% power-added-efficiency at 10 GHz.
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