Modeling of SiN inner spacer deposition in gate-all-around nanosheet FET process

The inner spacer process is a critical step in gate-all-around (GAA) nanosheet FET device fabrication and SiN is the most common material to be deposited after the indentation of the SiGe layer of alternative Si/SiGe layer structure. This gap filling process demands for highly uniform growth in order to minimize transistor variability, the lateral open feature of the indentation brings new challenges to conventional deposition technologies such as low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). In this work, we propose an analytical model of SiN deposition to predict the profile evolution of both LPCVD and PECVD, which can help process tuning and understand the influence of the multi-layer geometry and process condition on inner spacer growth performance in a more efficient and economical way. Experimental results reveal that the filling effect of LPCVD is significantly better than that of PECVD, simulation results also validate this. We also compare simulations with experiments, by comparing the model output with original SEM image, satisfactory matching between the two profiles demonstrates the validity of this model. Moreover, we set the SiGe layer thickness to be 10nm, 20nm and 30nm, and SiGe indentation as 10nm, 30nm and 50nm. Simulation reveals that the geometry has significant impact on the deposition performance. When the indentation is less than 10nm, both LPCVD and PECVD exhibit good SiN coverage. However, when indentation is deepened from 10nm to 30nm and 50nm, for PECVD, void firstly forms in 10nm thick SiGe layer and the necking effect tends to form larger void in 20nm and 30nm thick SiGe layers. For LPCVD, however, SiN grows more uniformly within and outside the cavity, and only very narrow gaps form in the cavity.