Noise Analysis in Comparator Circuits

In this paper, a way for analyzing noise processes in comparators is presented. Noise has a significant impact on the correct operation of the comparator and on different devices based on it, for instance on ADCs. The comparator is considered as a linear time-varying system; therefore, noise analysis is carried out in the time domain. General expressions are obtained for determining the variance of the output noise power of comparator. As an example, architecture of single- and double-tail comparators are considered, and expressions of the input and output noise are found. PSS/Pnoise modeling was performed and the results were compared with the measured ones.