Highly selective isotropic chemical dry etching for gate-all-around devices: nanosheet, forksheet and complementary FETs

For enabling better electrostatic control of short channel devices, gate-all-around (GAA) nanowire/nanosheet (NW/NS) field-effect transistors (FETs) may replace FinFET in 3nm logic technology node and beyond. Horizontally stacked NW/NS FETs are especially promising due to its excellent electrostatics, short channel control, increased active width, and gate length scaling. In order to enable further scaling of GAA FETs, imec has been developing forksheet (FS) FET as well as complementary FET (CFET). For the manufacturing of FS and CFETs, there are several new challenges which require isotropic and selective etching. In this work, we have been developed chemical isotropic dry etching for the several key process steps along with the integration flow, including Si/SiGe superlattice fin reveal, dielectric wall formation, local SOI formation, SiGe cavity etch as well as the dielectric etchback for the inner spacer formation, dummy gate removal and SiGe selective etch for the Si channel release