Can pin access limit the footprint scaling?

If pin density exceeds a certain threshold, pin access becomes a challenge for inter-cell signal routing and increasing the number of metal layers cannot improve routability. CMOS and FinFET layouts may never reach this threshold, but Vertical Slit Field Effect Transistor (VeSFET) ICs may exceed it. We demonstrate that VeSFET layouts are still routable within footprint using two-sided routing which achieves better wire length and via usage than one-sided routing with or without white space inserted.