Design consideration of gate driver circuits and PCB parasitic parameters of paralleled E-mode GaN HEMTs in zero-voltage-switching applications

This paper designed the gate driver circuits and optimized the PCB layout in a 7.2kW battery charger using paralleled GaN HEMTs. 650V/60A enhancement mode GaN HEMTs provided by GaN Systems Inc are adopted. To optimize the switching performance of paralleled GaN HEMTs with low loss and high reliability, effects of parasitic inductance and capacitance are modeled and analyzed. Through cancelling the flux in the commutation loop, the power-loop parasitic inductance is reduced to only 0.7nH, which significantly decreases the electrical stress in the switch turn-off process. A diverse-parameter gate driver design has been proposed to achieve the reliable switching off. The Finite-Element-Analysis and Spice simulation show our current design could effectively suppress the voltage overshoot and gate-drive ringing on HEMTs. Experiments were carried out on both double pulse test platform and the 7.2kW charger to verify the proposed design strategy.