Tunneling Dielectric Thickness‐Dependent Behaviors in Transistors Based on Sandwiched Small Molecule and Insulating Layer Structures

Abstract This work demonstrates the floating gate devices featuring a small molecule‐insulator‐small molecule‐insulator sandwiched structure, where the versatile electrical characteristics can be achieved depending on the thickness of the intermediate parylene tunneling dielectric layer (TDL). For the thin parylene layer of 15 nm (parallel DNTT channel transistor), channel also forms in the lower DNTT layer, allowing hole carriers to tunnel through the parylene TDL. The parallel DNTT channel transistor exhibits electrical characteristics similar to a conventional DNTT transistor with the increased contact resistance due to the presence of the intermediate parylene layer. When the parylene TDL is slightly thicker to be 45 nm, negative differential transconductance followed by current saturation behavior is observed, due to tunneling through the parylene TDL. Finally, photomemory is demonstrated with the sufficiently thick parylene layer (≈80 nm), where hole carriers injected from the electrode cannot tunnel through the parylene TDL, allowing the lower DNTT layer to act as a floating gate for the photogenerated charge carriers. This photomemory shows programmability under the light illumination with the specific wavelength as well as the robust retention and endurance characteristics. Furthermore, the photomemory has been successfully implemented on flexible paper substrates.