Optimum design for a two-stage CMOS I/O ESD protection circuit

In industry, the design of CMOS ESD (electrostatic discharge) protection devices and circuits has been approached empirically. In this work, we propose an optimization methodology for a typical two-stage CMOS I/O protection circuit based on simulation. We have identified two kinds of design, namely resistor-limited and NMOS-limited, and demonstrated that the isolation resistor design is the key to the circuit's protection level and performance.