Design rule optimization for via layers of multiple patterning solution at 7nm technology node

In the early stage of technology node definition and process development, design house owns abundant logic patterns resources and is able to offer fab more potential hotspots to do process window check, accelerating design rule qualification, feedback and optimization. A systematic methodology has been put forward to detect potential hotspots categories and modify related design rules with very insufficient process information for fabless side. It is efficient to conduct the study on a small number of patterns which can be treated as the typical of the whole physical design. Hence the physical design can be managed as a library and grouped by specific pattern signature for every layer. Based on the connectivity of source drain layers and local-interconnect layers, via0, under the first metal layer, is adopted litho-etch (LE) x4 on 193i scanner as the lithography solution. The experiment is carried out on the via0 layer. With consideration of minimum size and multiple limitations of other layers in design rule, systematic pattern analysis, fuzzy pattern search for low NILS, high MEEF and large PV bands have been combined to optimize the related design rules.