Improved Threshold Voltage Instability in 4H-SiC MOSFETs with Atomic Layer Deposited SiO<sub>2</sub>

This study reports the electrical characteristics and reliability of the atomic layer deposited SiO 2 on the 4H-SiC substrate. By controlling the thickness of SiO 2 in each ALD cycle, improved device properties like mobility and gate leakage were obtained as compared to the single deposition. Moreover, the optimized process dramatically reduces the threshold voltage shift under positive and negative bias stresses. This improvement can be attributed to the effective removal of unreacted metal-organic precursors, active traps, and broken bonds in the ALD SiO 2 dielectrics as well as reduction in interface state density at SiC/SiO 2 interface.