Predicting overlay mark performance based on semiconductor process emulation and optical simulation

Predicting the best preforming overlay marks for a set of layers in a new technology process flow would provide a powerful tool, which could potentially streamline the time consuming measurement process search for the optimal overlay mark. This is challenging because integration of the next generation of transistors and interconnects is becoming increasingly complex, so evaluating overlay mark performance in isolation yields partially valuable results. We show how process emulation can be used to evaluate overlay marks in conjunction with optical simulations for the critical patterning levels, and only the marks that perform well in simulation are allowed on the final mask, thereby predicting the best overlay marks for a particular technology. To make this methodology useful, it is important to cater each analysis to the specific materials being used, their optical properties, and the integration scheme of the technology. This is done as follows: (a) the optical properties of the materials being used are extracted using standard metrology tools, (b) the process flow of an existing technology is emulated, (c) an initial optical model is created with the inputs for settings like wavelength and focus form the metrology tool configuration, (d) the images from the overlay tool for the existing technology are analyzed to calibrate for unknowns such as numerical aperture and coherence, and finally, (e) the calibrated model is used on future technology flows to evaluate the performance of overlay marks. We will illustrate the validity of this methodology using specific examples and highlight its predictive capability.