Complementary 25 V LDMOS for analog applications based on 0.6 μm BiCMOS technology

A complementary 25 V LDMOS for analog applications based on 0.6 /spl mu/m BiCMOS technology has been developed. The n-channel LDMOS has two-step shallow n-implant layers which achieve low on-resistance and large safe operation area (SOA). The n-channel and p-channel LDMOS achieve high on-state breakdown voltages of 33 V and 50 V, respectively, for a gate voltage of 5.0 V. The values of specific on-resistance are 27.5 m/spl Omega//spl middot/mm/sup 2/ for n-channel and 111 m/spl Omega//spl middot/mm/sup 2/ for p-channel LDMOS.