PMOS逻辑
NMOS逻辑
可制造性设计
材料科学
薄脆饼
光电子学
频道(广播)
平版印刷术
晶圆规模集成
电气工程
电子工程
纳米技术
晶体管
工程类
电压
作者
Chelsey J. Dorow,Tom Schram,Quentin Smets,K. P. O’Brien,Kirby Maxey,Charlie Lin,Luca Panarella,B. Kaczer,Naimul Arefin,A. Roy,R. Jordan,Adedapo A. Oni,Ashish Verma Penumatcha,Carl H. Naylor,Mahmut Sami Kavrik,Dáire J. Cott,B. Graven,Valery V. Afanas'ev,P. Morin,Inge Asselberghs
出处
期刊:Technical digest
[Institute of Electrical and Electronics Engineers]
日期:2023-12-09
卷期号:: 1-4
被引量:40
标识
DOI:10.1109/iedm45741.2023.10413874
摘要
Rapid progress in fundamental understanding and development of 2D channel materials has yielded significant advances in contact resistance, gate oxide quality, and channel mobility, revealing opportunities for the future of Moore’s Law using highly-scaled 2D CMOS. We now scale up to 300 mm, for the first time, both NMOS and PMOS 2D transistors using today’s leading TMD candidates: MoS2, WS2, and WSe2. Our MoS2outperforms WS2as NMOS transistor due to higher mobility and lower contact resistance. WSe2multi-layers show high PMOS on-currents up to 200 μA/μm for larger grain size films. Larger TMD grain sizes outperform smaller grains for both NMOS and PMOS with up to 10× higher on-currents and steeper SS, identifying single crystal mono-layer channel uniformity as a paramount obstacle toward performance enhancement and reduced variation.
科研通智能强力驱动
Strongly Powered by AbleSci AI