Enhanced VDMOS design with reduced parasitic effect

This work provides a way to reduce the parasitic effect that is present in ordinary power MOSFETs. In this device, source and drain doping is eliminated from the design process using charge plasma technique leading to the reduction of parasitic effects due to parasitic bipolar junction transistor (BJT) from the device. A vertical metal oxide-semiconductor field effect transistor (VMOS) is proposed by employing this technique. It is simulated and compared with the conventional vertical double diffused metal-oxide-semiconductor field effect transistor (VDMOS). In this work, the proposed VMOS is also tested with various materials that can be used for plasma formation. When compared to the conventional VDMOS, the proposed VMOS exhibits 54.21% increment in breakdown voltage, 55.03% reduction in ON-resistance and approximately two times of the drain current density.