Defect-Based Empirical Model for On-State Degradation in Sub-20-nm DRAM Periphery pFETs Under Arbitrary Condition

This work investigates the ON-state degradation under arbitrary stress conditions for periphery pFETs fabricated in the sub-20-nm DRAM technology. Three types of traps are identified, including the interface states, the oxide hole traps, and the oxide electron traps. By analyzing the time dependence, stress dependence, and lateral position, the generation mechanism for each type of trap is revealed, based on which a defect-based model was established. We proposed an effective model parameter extraction strategy and, thus, avoided overfitting. The predictive capability of the proposed model is further verified across the full bias regions at lower voltage conditions, including operating conditions. Finally, based on the model, the contributions of different types of traps to the degradation can be derived throughout the device's entire lifetime. The work paves ways to link the defects to the device's long-term reliability, which can be helpful for future process optimization and device/circuit co-optimization in DRAM peripheral circuits.