First-principles study of metal-semiconductor contacts and quantum transport simulations for 5.1-nm monolayer MoSi2N4 devices

The semiconductor industry has been facing obstacles in designing low-power (LP) nanoelectronic devices due to the lack of accurate theoretical simulations and low-resistance contacts of heterojunctions. Here, based on experimental data, we discover that the generalized gradient approximation using the Fritz Haber Institute pseudopotential accurately describes the lattice constants and electronic properties of monolayer ${\mathrm{Mo}\mathrm{Si}}_{2}{\mathrm{N}}_{4}$. It is further confirmed that this method is also applicable to characterize the electrical contact properties and device transport characteristics of metal$/{\mathrm{Mo}\mathrm{Si}}_{2}{\mathrm{N}}_{4}$ heterojunctions (where metal includes $\mathrm{Sc},\phantom{\rule{0.2em}{0ex}}\mathrm{Bi},\phantom{\rule{0.2em}{0ex}}\mathrm{Ag},\phantom{\rule{0.2em}{0ex}}\mathrm{Al},\phantom{\rule{0.2em}{0ex}}\mathrm{Ti}$, graphene, $\mathrm{Cr}$, $\mathrm{Fe},\phantom{\rule{0.2em}{0ex}}\mathrm{Cu},\phantom{\rule{0.2em}{0ex}}\mathrm{Co},\phantom{\rule{0.2em}{0ex}}\mathrm{Au},\phantom{\rule{0.2em}{0ex}}\mathrm{Pd},\phantom{\rule{0.2em}{0ex}}\mathrm{Ni},$ and $\mathrm{Pt}$). Calculations show that various bulk metal/${\mathrm{Mo}\mathrm{Si}}_{2}{\mathrm{N}}_{4}$ heterojunctions exhibit n-type Schottky barrier contact features, and it is possible to achieve 100% carrier injection for ${\mathrm{Mo}\mathrm{Si}}_{2}{\mathrm{N}}_{4}$ with $\mathrm{Sc},\phantom{\rule{0.2em}{0ex}}\mathrm{Ag},\mathrm{Ti},\mathrm{Pd},$ and $\mathrm{Pt}$ contacts. Using the Schottky-Mott rule and quantum transport simulation, a strong Fermi-level pinning effect at the metal$/{\mathrm{Mo}\mathrm{Si}}_{2}{\mathrm{N}}_{4}$ interfaces is observed, and $\mathrm{Sc}$ is identified as the best metal electrode. The 5.1-nm p-i-n field-effect transistor (FET) with $\mathrm{Sc}$ electrodes can meet the off-state current requirement of the 2013 International Technology Roadmap for Semiconductors standard for high-performance and LP FET devices. By employing a high-k gate, the on-state current for the undoped LP device can be improved by 2 orders of magnitude, and its high on:off ratio is up to 3 \ifmmode\times\else\texttimes\fi{} ${10}^{6}$. These findings provide insights into the metal/${\mathrm{Mo}\mathrm{Si}}_{2}{\mathrm{N}}_{4}$ interface behaviors and provide a theoretical reference for designing ${\mathrm{Mo}\mathrm{Si}}_{2}{\mathrm{N}}_{4}$-based nanoelectronic devices by selecting suitable electrodes with low contact resistance.