A compact model of analog RRAM for neuromorphic computing system design

The emerging memory such as resistive random access memory (RRAM) is considered as a promising solution to emulate the synapse for neuromorphic computing. It is still difficult to evaluate the performance and optimize the design of RRAM-based neuromorphic system due to the intrinsical device characters. Here, the bidirectional analog and multi-level compact models are proposed to cover the tuning fluctuations for on-chip training and inference processes. Both the analog and multi-level simulated results are experimentally verified on 1-Kbit RRAM array.