Split-Gate Flash Memory: from Planar to 3D

This review addresses the growth of split-gate flash memory technology, which has matured over the past few decades, and is now entering the domain of non-planar structure. The technology was first introduced as a groundbreaking technology because of its high programming efficiency, low power consumption, over-erase immunity, and superior reliability. Though its journey of continued scaling has not been without a hitch, the third and latest generation of the embedded SuperFlash (ESF) has now been the industry standard for embedded devices. Onward from the first ESF3 cell, innovations allowing the evolution of the split-gate structure includes the High-K Metal Gate (HKMG) technology and gate structure engineering to improve device performance. Ultimately, in today's direction of cell shrinking, the 3D FinFET architecture is incorporated in the 16/14 nm design of the split-gate memory cell structure to allow further scaling of the technology.