A study of 90nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure

In this paper, 90 nm MOSFET subthreshold hump characteristics are reported for the first time by using a newly developed MOSFET array test structure, which has small-scale DUTs with a new layout pattern, in order to eliminate the influence of gate leakage and off leakage on measured MOSFET parameter data such as Vth, Ion, subthreshold slope, etc. It is confirmed that a subthreshold hump occurs at random in an array, and the hump occurrence percentage differs with chips in a wafer. By extracting the hump variation with a MOSFET array, it is possible to estimate accurately and reduce the standby-current in logic LSI chips.