Optimizing RDS(on) of Dual-Chip Power MOSFET by Fan-out Panel Level Packaging (FOPLP)

Fan-out packaging (FO-packaging) is considered one of the important technical means to continue and surpass more than Moore's law due to its advantages such as cost reduction, low profile, excellent electric properties, and excellent heat dissipation. As a type of FO-packaging, fan-out panel level packaging (FOPLP) has the advantages of a low single package cost, high effective utilization of carrier board, and high packaging efficiency. In this study, a dual-chip power device MOSFET was designed and fabricated based on FOPLP technology, which consists of pads, solder, chips, circuits, and epoxy molding compound. Simultaneously realizing the electrical interconnection of the entire device through blind vias. Compared with traditional wire bonding, the static drain-source on-resistance (R DS(on) ) of MOSFET based on FOPLP technology was reduced by about 10%. Hence, the MOSFET based on FOPLP can effectively reduce R DS(on) .