Implementation of the Logistic Map with FPGA using 32 bits fixed point\n standard

This article presents a design of the logistic map by means of FPGA (Field\nProgrammable Gate Ar-ray) under fixed-point standard and 32-bits of precision.\nThe design was carried out with Altera Quartus platform. The hardware\ndescription language VHDL-93 has been adopted and the results were simulated by\nmeans of Altera ModelSim package. The main of the project was to produce a\ncha-otic system with a low energy and time cost. Using the VHDL, it was\npossible to use only 1439 logical gates from 114480 available. The Lyapunov\nexponent has been calculated with good agreement with literature reference,\nwhich shows the effectiveness the proposed method.\n