Copper clip package for high performance MOSFETs and its optimization

Copper clip package plays a critical role in meeting the increasing requirement for lower total device resistance RDS(on), higher power density and high frequency switching applications. The copper clips replaced traditional wirebond interconnect for high performance MOSFETs by providing lower resistance and inductance than multiple wirebonds and improves thermal performance. This paper will discuss about the research and development efforts from different stages of package's development from simulation, analysis and process optimization of array clips assembly of this package. Comprehensive mechanical, thermal and electrical analyses are performed for a power module with stringent requirement. Thermal simulations are performed to study the impact of attachment voids and the thermal advantages of copper clip. Electrical simulation shows the comparison of copper clip over multiple copper wires. Design for process optimization such as array bonding, high speed bond head and high performance clip singulation system are discussed as well. Key learning from this study can be used to formulate database and guidelines for upfront product enhancement, reduce the design-to-implementation cycle time, identify high risk before fabrication and troubleshooting during production. Collaborative approach with simulation can save time and resources, hence increasing efficiency and reducing cost as well as development cycle time.