Synthesis and Simulation of a 32Bit MIPS RISC Processor using VHDL

The main objective of the project is to design and simulate 32Bit MIPS (Microprocessor Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using VHDL (Very High Speed Integrated Circuit Hardware Description Language). In this paper, we analyze Instruction fetch module, Decoder module, Execution module which includes 32Bit Floating point ALU, Flag register of 32Bit, MIPS Instruction Set, and 32Bit general purpose registers and design theory based on 32Bit MIPS RISC Processor. Furthermore, we use pipeline concept which involves Instruction Fetch, Instruction Decode, Execution, Memory and Write Back modules of MIPS RISC processor based on 32Bit MIPS Instruction set in a single clock cycle. All the modules in the design are coded in VHDL, as it is very useful language with its concept of concurrency to cope successfully with the parallelism of digital hardware. Finally, Synthesis and Simulation of the design is done in XILINX 13.1i ISE Simulator.