High Performance and Robust Oxide-Semiconductor Channel Transistor DRAM with Multi-tiered Architecture

We have successfully demonstrated the world's first backend-of-line (BEOL)-integrated, multi-tiered horizontal cell stacked DRAM architecture—featuring a double-channel indium gallium zinc oxide (IGZO) FET—proving its feasibility through experimental validation on a 12-inch wafer platform. The fabricated IGZO-based double-channel access transistor achieved an on-current (Ion) of 60.9 µA/μm at Vds=1.0V and Vgs=2.0V, a positive threshold voltage (Vt=0.28V) with a subthreshold swing of 80 mV/dec, and an off-current (Ioff) below 1fA/μm (test-limited). Additionally, the device demonstrated excellent reliability, a dynamic PBTI testing indicated a maximum gate voltage (Vgmax) of 1.66V ensuring a 10-year lifetime at 100°C with ∆Vt <100 mV. The projected TDDB maximum gate voltage is 3.62 V for 10-years lifetime at 100°C. These performance gains are attributed to optimized strategies, including proper IGZO composition, interface engineering, gate insulator (GI) and gate electrode film stack design, and reduced source/drain contact resistance. The breakthrough in this innovative architecture with addresses conventional scaling limitations while maintaining key electrical and reliability thresholds, offering a promising path for future DRAM innovation.