跨导
光电子学
材料科学
单层
逻辑门
晶体管
阈下斜率
降级(电信)
场效应晶体管
阈值电压
频道(广播)
十八烷基三氯氢硅
电子工程
MOSFET
钥匙(锁)
纳米电子学
电气工程
和大门
纳米技术
阈下传导
栅氧化层
氧化物
接触电阻
NMOS逻辑
作者
Jun Cai,Hao-Yu Lan,Yuanqiu Tan,Zhihong Chen,Joerg Appenzeller
标识
DOI:10.1109/iedm50572.2025.11353892
摘要
In this work, we present the first demonstration of ultrathin (0.3 nm) contact extensions in ultra-scaled dual gate (DG) MoS2FETs to address short-channel effects (SCEs) induced by ‘contact gating’ - a key limitation in existing 2D FETs. The ultra-scaled DG devices feature channel lengths (LCH) down to 20 nm and a combined equivalent oxide thickness (EOT) of 0.75 nm, with on-currents reaching 460 μA/μm and maximum transconductance values reaching 206 μS/μm at VDS=1 V, the highest reported for 20 nm channels. Moreover, due to the ultra-thin contact extensions, our devices exhibit near immunity to SCEs. The off-state performance specs outperform prior reported data on 20 nm FETs, with minimal subthreshold slope (SS) degradation at 20 nm (< 25% increase compared to long-channel device), SS= 97 mV/dec, DIBL=30 mV/V, and a near zero threshold voltage. This work marks a key step toward aggressively scaled logic devices based on 2D materials.
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