A 0.0025mm2 8-bit 70MS/s SAR ADC with a Linearity-Improved Bootstrapped Switch for Computation in Memory

Resistive Random Access Memory (ReRAM)-based analog computing-in-memory (CIM) is a promising approach to tackle the memory wall problem in data-intensive operations. However, in ReRAM-based analog CIM, the area and energy overhead imposed by DACs and ADCs hinders the potential of CIM. To alleviate this problem, an 8-bit 70 MS/s SAR ADC with a linearity-improved bootstrapped switch and a transconductance-enhanced dynamic comparator is presented in this work. All active devices are placed beneath the capacitors to save the area, resulting in a core area of 0.00255 mm ² in a 110 nm CMOS technology. A proper CDAC switching scheme, transconductance-enhanced comparator, and custom-designed DFF are implemented to improve energy efficiency and speed. Post-layout simulation demonstrates that it achieves 46.22 dB SNDR near Nyquist frequency while consuming 553 uW of power at 1.2 V supply, which yields 47.26 fJ/Conv FoM.