导电体
互连
模具
集成电路封装
材料科学
电气工程
电子工程
计算机科学
光电子学
复合材料
工程类
集成电路
电信
作者
Serine Soh Siew Boon,Soon Wee Ho,Norhanani Jaafar
标识
DOI:10.1109/eptc59621.2023.10457718
摘要
Through-Mold Interconnects (TMI) have been widely adopted and integrated into Fan-out Wafer Level Packaging (FOWLP) for semiconductor packaging technology. With the increasingly I/O counts and higher performance applications, the incremental density of lateral and vertical interconnects is essential to enhance the interconnections development in circuit miniaturization. This paper will discuss an alternative cost-effective and versatile approach, conductive paste via-filling, to form vertical interconnections between the embedded electrical routes to the external connections of the FOWLP. This approach promotes the ability in forming of vertical interconnections with greater critical dimension and depths, as compared to the existing Through-Mold Interconnect (TMI) formation methods.
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