THERMO-ELECTRICAL CO-DESIGN OF THREE-DIMENSIONAL INTEGRATED CIRCUITS: CHALLENGES AND OPPORTUNITIES

This paper focuses on the thermal challenges in three-dimensional (3D) chip stacking, which is poised to become the next packaging paradigm in the electronic industry. While this paradigm provides significant improvements in device density, interconnect delays, and system integration, it is expected to lead to higher heat densities along with decreased access of chip hot spots to air-cooled heat sinks. Excessive chip temperatures are a well-known culprit leading to performance and reliability loss as well as higher leakage power. This paper investigates the advantages and challenges imposed by interlayer microfluidic cooling to address the thermal needs of 3D integrated circuits (ICs). We present a brief review of the emerging 3D form factors and application of microfluidic cooling followed by several case studies that quantify the potential improvement obtained by co-design of the thermal and electrical aspects of the 3D ICs. We underscore the need for better unification of the thermal and fluidic aspects of the system into an integrated co-design environment that enables designers to estimate the impact of the cooling solutions on the electrical aspects and vice versa. Such a co-design approach would be imperative for unlocking the high performance and energy efficiency of 3D ICs.