A 48x OSR 105.4-dB SNDR 24-kHz BW CT Zoom ADC with Reset Tri-level DWA and On-chip Negative-R Calibration

Battery-powered high-performance audio applications call for energy-efficient ADC with high dynamic range (DR) and SNDR across the entire audio band (ADB). Continuous time (CT) sigma-delta modulators (SDM) are widely exploited due to their implicit anti-aliasing (M) and easy-driven nature. Despite the bloom of energy-efficient integrators [1]–[6], their high SNDR and DR rely on a large oversampling ratio (OSR, ≥100x) [2]–[6] and/or high supply voltage [1], [2], [4], [6] $(\geq 1.8\mathrm{V})$. This results in significant power consumption from the drivers as well as reference of DACs, and the op-amps for high unit-gain bandwidth (UGBW) in integrators [1], [4], [5]. Associated high sampling rate (Fs) also induces large overheads related to the clock buffering, generation, DAC switching and decimator, which exacerbate the supply/ground noise and hence occupy extra areas for isolation/decoupling. This design relieves the need of high OSR by the presented reset tri-level DWA (RST-TDWA). It is integrated into an energy-efficient CT-Zoom (CTZ) ADC featuring an efficient loop filter (LF) with its first integrator assisted by the presented tri-path chopped negative-R (TPC-NR), which allows a low-supply-operating ADC. The fuzz issue in the CTZ is addressed by the proposed passive feedforward (FF) scheme. Highly hardware-sharable on-chip negative-R and DAC calibrations are introduced, securing ≤2dB SNDR degradation over PVT. The 48x-OSR prototype exhibits a 105.4-dB SNDR@1-kHz and an <0.5-dB SNDR loss across the entire ADB. Drawing 208-µW from a single 1.2-V supply, it yields a 186.0dB FoMsNDR.