Large-scale VLSI mask optimization: a survey

As Moore’s law has advanced, large-scale VLSI manufacturing has raced to keep pace with ever-shrinking feature sizes and tighter process windows. Within this context, mask optimization, encompassing optical proximity correction (OPC), sub-resolution assist features (SRAFs) and inverse lithography technology (ILT), has become a central enabler of pattern fidelity, yield, and cost at advanced nodes by jointly compensating optical and process distortions. This survey reviews recent progress in large-scale VLSI mask optimization, emphasizing methods that make full-chip deployment practical. We first cover accelerated lithography modeling, including physics-based solvers and learning-based surrogates that preserve printability signals while reducing simulation latency. We then examine modern mask optimization methods, spanning improved numerical ILT advances and emerging machine learning-driven approaches that together enhance solution quality and runtime. Next, we discuss full-chip mask optimization frameworks that tackle the scale and manufacturability of real-world designs. Finally, we conclude with open challenges and research opportunities in the field. We hope this survey provides a useful reference for future research and industrial adoption of large-scale VLSI mask optimization.