Image Recognizing Based on the Architecture Integrated with CIM and CIS

CMOS image sensor (CIS) technology has made significant development in integrated circuits (ICs), offering competitive advantages in on-chip functionality, power consumption, and cost. However, it also faces some challenges, such as circuit complexity and processing speed. In recent years, computation-in-memory (CIM) architecture shows great advantages because it reduces data movement between memory and processing unit significantly. In this work, we propose an architecture integrated with CIS and CIM. The CIS pixel consists of a diode and three transistors, which is modified based on the traditional CIS pixel circuit. In the CIM block, a 4-bit 6-T SRAM and four multiplication transistors are used to store weight and perform product of weight and input, respectively. Signals from the CIS pixels are sent to the CIM block for on-chip image processing. We design and simulate an 8×8-pixel array and a CIM array with standard 180nm CMOS technology. This design achieves 2000/ps processing speed, 82.5% recognizing accuracy, presenting a promising solution for Non-Von-Neumann architecture devices in many applications.