A Lightweight Hardware Accelerator for Fixed-Point Least-Squares Estimation in RISC-V SoCs

Solving overdetermined linear systems is a fundamental computational challenge in real-time embedded applications, such as image processing, autonomous navigation, and robotics. In these domains, parameter estimation frequently requires resolving sensor data with high precision and low latency. Since the direct inverse of a non-square matrix is not applicable, the Least Squares Method is utilized to minimize observation errors. Traditional software-based implementations on generalpurpose processors often fail to meet the stringent latency and power constraints of edge devices. This paper presents a hardware/software co-design methodology to accelerate the Least Squares solution, specifically targeting small-scale, fixedsize parameter estimation problems (e.g., 4-by-4 state vectors). Following an algorithmic analysis, the Modified Cholesky method was identified as the optimal, square-root-free approach for hardware implementation. The proposed custom Verilog accelerator is integrated as a memory-mapped peripheral within a RISC-V System-on-Chip (SoC). We utilize a real-world Global Navigation Satellite System (GNSS) dataset as a case study to validate the workflow. Experimental results demonstrate a 3.74x to$4.21 x$speedup compared to highly optimized software-only implementations, proving the architecture's viability for real-time edge computing.