Revisiting thermal effects in submicron CMOS-SOI transistors

In this study we report measurements and modeling of true channel temperature of CMOS-SOI transistors. It is shown that the temperature rise is significant, above 100K, for transistors with applied power of ~0.1 milliwatt. The CMOS-SOI transistors were designed and fabricated with a standard partially depleted CMOS - SOI 0.18μm process. It is shown that the local heating of the channel carriers may result in higher temperatures than predicted by the conventional steady-state thermal analysis. Modeling based on channel's thermoelectric effects is applied to account for the observed local-heating. The results of this study have impact on circuit design and may be extended to regular CMOS submicron technology.