System-Level ESD Protection Design Using On-Wafer Characterization and Transient Simulations

A methodology for the design of circuits robust to system-level electrostatic discharge (ESD) stress is presented and verified with two case studies. The combination of on-wafer characterization and transient simulations enables the ESD designer to study the behavior of the component-level ESD protection design during system-level ESD stress with and without adding off-chip protection devices. The design of a system-level ESD protection solution can be verified long before IC packaging and even before the final system is built.